1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device having a non-porous film formed between a porous film and a barrier metal film, and relates to the semiconductor device.
2. Related Art
In semiconductor devices of recent years, device operation speed is limited by a delay in signal propagation through interconnects. A delay constant through an interconnect is represented by a product of an interconnect resistance and an interconnect capacitance. Therefore, copper (Cu), which has lower electrical resistivity, is employed for interconnects, and a porous material, which has lower relative dielectric constant than the conventional SiO2, is employed for an insulating interlayer formed between the interconnect layers, so that the operating speed of the device is increased.
A Cu multilayered interconnect is to be formed by manufacturing interconnects and vias by a damascene process. More specifically, first of all, an insulating film such as insulating interlayer and the like is formed on a semiconductor substrate. Then, an interconnect trench or a via hole (hereinafter referred to as a concave portion) is formed in the insulating film. Then, a barrier metal film is formed so as to cover an interior wall of the concave portion and further to cover the surface of the insulating film. Further, a Cu thin film serving as a seed layer is formed on the barrier metal film. Then, an electrolytic plating process is conducted by utilizing the Cu thin film as a cathode electrode to form a Cu film on the barrier metal film, so that the interior of the concave portion is filled therewith. Then, portions of the barrier metal film and the Cu film located in the outside of the concave portion are removed by a chemical mechanical polishing (CMP). By employing such method, the barrier metal film and the seed Cu film are partially remained only in the concave portion to form the interconnect or the via. In the above-described operation, the barrier metal film is provided between Cu and the insulating interlayer, for the purpose of preventing a diffusion of Cu into the semiconductor substrate, serving as an adhesion layer between the insulating interlayer and Cu, and further preventing an oxidization of Cu.
As described above, the interlayer insulating film is formed of a porous material having a relative dielectric constant, which is lower than that of conventionally employed SiO2. Therefore, when the barrier metal film or the Cu film is formed, materials composing these films may often be penetrated into an interior of a pore of the porous film (interlayer insulating film). In recent years, in order to improve a coating-ability of the barrier metal thin film, a deposition thereof by an atomic layer deposition (ALD) process is examined.
Nonetheless, the barrier metal easily penetrates into the pores of the porous film, since the ALD process generally provides higher step coverage. This phenomenon reduces the film thickness of the barrier metal film formed in the concave portion, and thus ability for preventing a diffusion of Cu into the insulating layer through the barrier metal film is reduced. Therefore, a reliability of transistor characteristics in the semiconductor device is reduced. Further, insulating properties such as a dielectric breakdown voltage are degraded by metals such as barrier metal or Cu penetrating in the interior of the pores in the porous film. Further, a leakage current—is increased between adjacent interconnects, thereby reducing a reliability in a signal propagation through the interconnect.
In such circumstances, a type of semiconductor device, which is capable of preventing the barrier metal formed by the ALD process from entering in the interior of pores of the porous film and thus preventing a reduction in the thickness of the barrier metal film, is expected.
Typical implementations of such semiconductor device shown in FIG. 8 are described in Japanese Patent Laid-Open No. 2000-294,634, Japanese Patent Domestic Publication No. 2004-535,065 for PCT International Application and K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma and Z. S. Yanovitskaya, Journal of Applied Physics 93 (11), pp. 8793-8841, 2003. A semiconductor device shown in FIG. 8 contains a semiconductor substrate 112 containing a semiconductor element, a via layer 132 formed over the semiconductor substrate 112 and Cu interconnect layer formed over the via layer 132. The via layer 132 shown in FIG. 9 is composed of an etching stopper 114, a porous film 116 and a protective film 118 stacked in this sequence. A concave portion is formed in the via layer 132, so as to expose a surface of Cu interconnect of the semiconductor substrate 112 in a bottom thereof. Furthermore, a viaplug 120 is formed in the concave portion. The viaplug 120 is composed of a non-porous film 124, a barrier metal film 128 and a Cu film 130. A non-porous film 124 that covers a side wall of the concave portion, a barrier metal film 128 that covers surfaces of the non-porous film 124 and a surface of Cu interconnect of the semiconductor substrate 112 exposed on the bottom of the concave portion, and a Cu film 130 that plugs the interior of the concave portion are formed in this concave portion. An interconnect layer 133 is formed on the via layer 132. A multilayered insulating film 134 contains the via layer 132 and the interconnect layer 133.
As a material for serving as the non-porous film 124, SiO2 is illustrated in Japanese Patent Laid-Open No. 2000-294,634, SixCy: Hz is illustrated in Japanese Patent Domestic Publication No. 2004-535,065 for PCT International Application, and SiO2, SiC and SiN are illustrated in K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma and Z. S. Yanovitskaya, Journal of Applied Physics 93 (11), pp. 8793-8841, 2003.
Further, a semiconductor device having a configuration, in which an insulating film fills an inside of a pore of a porous film exposed to an interior of a concave portion, is described in Japanese Patent Laid-Open No. 2004-193,326. It is described in Japanese Patent Laid-Open No. 2004-193,326 that non-porous polyallylether or SiOx (CH3)y is employed for forming such insulating film.
Nonetheless, there is a room for an improvement in the conventional technologies described above in terms of the following issues. In the processes described in Japanese Patent Laid-Open No. 2000-294,634, Japanese Patent Domestic Publication No. 2004-535,065 for PCT International Application and the above-described K. Maex et al., barrier metal or Cu is introduced in the interior of the pores in the porous film to reduce the insulation resistance of the porous film and to further cause a leakage current between adjacent interconnects, so that the reliability in the signal propagation through interconnects may be reduced. In particular, such tendency is considerable when the barrier metal film is formed by an ALD process.
In the process described in Japanese Patent Laid-Open No. 2004-193,326, the interior of the pores existing in the porous film exposed to the concave portion can not be fully filled with the insulating film, and therefore there is also a room for an improvement in such process, similarly in the technologies described above. Further, in the process described in Japanese Patent Laid-Open No. 2004-193,326, it is necessary to remove an unnecessary portion of the insulating film on the surface of the porous film after the operation of filling the inside of pores of the porous film, and therefore there is a fear that the process becomes complicated.